module sfm(
input        clk,
input        load1,//zhuang_zai_ji_shu_zhi_shang_sheng_yan
input [7:0]  sec_in,
input [7:0]  min_in,
input [7:0]  hour_in,

output reg[7:0] sec_out,
output reg[7:0] min_out,
output reg[7:0] hour_out,

output reg clk_day//chuan_ru_nyr_zuo_shi_zhong
);

reg clk_min,clk_hour;//jin_wei_biao_zhi

//sec_out
always@(posedge load1 or posedge clk)
   begin
        if(load1)  
             begin
               sec_out=sec_in;   
             end
       else if(sec_out==8'd59)
             begin
               sec_out=0;
               clk_min=1;
             end
       else 
             begin
                sec_out=sec_out+1;
                clk_min=0;
             end

   end


//min_out
always@(posedge load1 or posedge clk_min)
   begin
        if(load1)  
             begin
                min_out=min_in;   
             end
       else if(min_out==8'd59)
             begin
               min_out=0;
               clk_hour=1;
             end
       else 
             begin
                min_out=min_out+1;
                clk_hour=0;
             end

   end
   
//hour_out
always@(posedge load1 or posedge clk_hour)
   begin
        if(load1)  
             begin
                hour_out=hour_in;   
             end
       else if(hour_out==8'd23)
             begin
               hour_out=0;
               clk_day=1;
             end
       else 
             begin
                hour_out=hour_out+1;
                clk_day=0;
             end

   end
endmodule